FPGA and ASIC Verification

Hughes Systique Corp.'s (HSC) Hardware Design Services Center primarily focuses on cutting edge wireless/wireline technologies and provides complete solutions in the VLSI domain, meeting critical time-to market time-to-market demands of the customers with design reliability, scalability and upgradeability.

HSC offers comprehensive design and verification solutions in FPGA/ASIC. Our world-class Hardware Design Services Center brings you a wide range of design and verification services that encompass system specification definition, hardware and software partitioning, IP identification, RTL designing & verification, board level design & verification, system integration & testing and verification in Front End FPGA & ASIC. We have a talented pool of engineers who have experience in successfully executing different projects using the latest EDA tools and technologies.



Skill Sets

• Micro Architecture & RTL Design Services for FPGA / ASIC
  • System requirement generation and hardware-software partitioning
  • Micro-architecture design
  • RTL coding (Veirlog/VHDL)
  • FPGA Design Synthesis & Implementation
  • ASIC & SoC Design & Implementation
  
   
• Verification Services
  • Planning and Defining Test methodologies
  • Developing Verification Plans and Test benches
  • RTL simulations and validation
  • Test vector generation using System prototype
  • Development of Bus Functional Modules(BFM)
  • Formal Verification
  • Assertion Based Verification
  • Automated test environment setup with Perl, Tcl
  • Code coverage driven Verification
  • Gate level simulation or timing simulation
  • SoC Verification
  
   
• System Prototyping Services
  • System prototyping using MATLAB / C / C++ / System C / System Verilog
  • Conversion of Floating point models to Fixed point models
  • Validation of system prototype
  • Technology evaluation / Vendor selection
  • Identifying IP requirements if necessary
  • Performance Analysis
  • Generation of golden test vectors for RTL using the prototype
  
   
• Re-Engineering Services
  • Re-Target existing FPGA / ASIC designs to improve speed and optimize area
  • Conversion of DSP algorithms to RTL
  • Translation from ASIC to FPGA and FPGA to ASIC
  • FPGA prototyping for ASIC / SoC

EDA Tools Experiences

PARAMETER	CAPABILITIES
Design Complexity	Multi Million Gate, Multiple Clock Domains,
HDLs	Verilog, VHDL, System Verilog
FPGA Devices	Altera (Stratix / GX, Stratix2 / GX, Cyclone / 2, Stratix 3, Hardcopy/II), Xilinx (Virtex 5 LXT, SXT, Virtex/2/Pro, Virtex4, Spartan/2/3), Actel (Fusion),
Simulation Tools	ModelSim SE/MXE/PE, NCSim, VCS
Synthesis Tools	Xilinx ISE 10.1, Quartus II, Synplify Pro, FPGA compiler, Synopsys Design compiler
Linting Tools	Explore RTL, LEDA, SpyGlass, HDLint, nLint, BlackTie
Code Coverage Tools	vNavigator, HDLscore, SureCov, Modelsim
Re-usable Blocks	FFT, Viterbi, CORDIC
Place & Route	Xilinx ISE, Quartus

Technology Experience

Technology	Experience
Wireless Baseband	Layer 1 baseband implementation for LTE, WiMAX, 2G & 3G technologies
Satellite Communication	RTL design, firmware development, integration and testing for satellite base station Board level verification
Wireline Communication	SONET, SDH, PDH, Ethernet over SDH development ITUT standards G703, G704, G707
Bus Interfaces	I2C, USB, UART, SRIO, SERDES etc OBSAI RP3/RP3-01, AMBA – AXI/APB, PCI, DDR2
Multimedia	Video Codecs (H.264, AVC), Speech Codecs, Image and Video Processing