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| RTL implementation of L1 datapath as per 3GPP LTE Rel 8 specifications |
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Key Technologies : 3GPP LTE, Layer 1, Layer 2, FPGA, DSP
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Abstract: HSC developed a Layer 1 processing solution targeted on FPGA. The RTL code was developed to meet the throughput and latency requirements of 3GPP LTE.
The RTL blocks for layer 1 processing were developed to be used as a coprocessor which can be easily integrated with a processor to schedule layer 1 processing.
Customer Benefits:
- Flexible system design that could be adopted to different platform
- Generic Verilog RTL coding for module development
- Requisite API definition for MAC-PHY Interface
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