DSP

GMR 3G UT PHY development on SDR platform
Key Technologies : GMR1-3G CAI, SDR, SIMD

Abstract: The Project aims at implementation of the complete Physical Layer and Access Stratum based on the GMR-1 3G specifications on the Infineon's (IFX) SDR20 platform. The scope includes development and porting the baseband modules onto SIMD, porting of AS onto Thread-X RTOS, development of L1 state machine layer which will run on ARM and SIMD.
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LTE baseband development
Key Technologies : 3GPP LTE, baseband

Abstract: Generic fixed point C implementation available for all baseband routines Integrated on TI platform and can be ported on any other processor A large pool of trained engineers available with sound understanding of layer 1 procedures and processor implementation experience Abstract: HSC has developed a PoC LTE layer 1 solution targeted on TI platform.
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Codec development and Framework
Key Technologies : EVRC-B, WB-AMR, G 722.1, H.624

Abstract: HSC has a vast experience in Multimedia codec development and optimization on various processors. We developed the multimedia framework where we have integrated the developed and optimized codecs in the framework. The codecs were optimized to meet the MCPS and Memory requirement.
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3G baseband development

Abstract: This project was to develop the baseband receiver using TI C64X DSP and Xilinx FGPGA. We developed the front end receiver algorithms including rake receiver. We also developed the state machine and scheduler for Baseband processing which was placed in ARM 9.
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DVB-s2 satellite modem
Key Technologies : RTL Design, DVB Satellite Modem, Xilinx Virtex 5

Abstract: The architecture below comprises of a Broadband VSAT system consisting of FPGAs having interface with DSP & custom SoC. The Adaptive coding and modulation (ACM) feature means that the coding (FEC rate) and modulation DVB-S2 outbound carrier can be dynamically modified to optimize the performance per terminal.
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3G Layer 1 development
Key Technologies : RTL Design, 3G.

Abstract: This project was to develop a baseband receiver using TI C64X DSP and Xilinx FPGA. HSC developed the front end receiver algorithms including rake receiver. To test this HSC developed the UT simulator apart from test vectors generated through MATLAB. Finally to meet the requirement of number of users and throughput HSC also incorporated optimizations in FPGA and DSP. Customer Benefits: Provided reusable components for FPGA. System engineers helped with smooth integration HSC provided DSP, FPGA, System, Algorithms so that the customer could treat HSC as a one stop shop and not have to mediate between multiple customers.
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