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Semiconductors

HSC offers system architecture, software/hardware partitioning, design/development and verification services for FPGA and DSP cores from vendors like TI, Xilinx, Altera, and AMCC. Development of media frameworks and customization/optimization of codecs, reference design development are some of the services we offer in this vertical.

White Paper/Open Sources related to Semiconductors

IPv4 to IPv6 Protocol Translator for Multicast

Abstract: HSC is pleased to announce an open source code which has support for protocol translation of IGMPv3 to MLDv2. This translation can be used on a IGMP/MLD relay network node which has a IPv4 network on the subscriber side and an IPv6 network on network side or vice versa.The implementation shall allows the relay node to signal to next hop multicast router residing in an IPv6 network that there are interested listeners resident in an IPv4 network or vice versa.
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Case studies related to Semiconductors

GMR 3G UT PHY development on SDR platform Abstract: The Project aims at implementation of the complete Physical Layer and Access Stratum based on the GMR-1 3G specifications on the Infineon's (IFX) SDR20 platform. The scope includes development and porting the baseband modules onto SIMD, porting of AS onto Thread-X RTOS, development of L1 state machine layer which will run on ARM and SIMD. Read more...
LTE baseband development Abstract: Generic fixed point C implementation available for all baseband routines Integrated on TI platform and can be ported on any other processor A large pool of trained engineers available with sound understanding of layer 1 procedures and processor implementation experience Abstract: HSC has developed a PoC LTE layer 1 solution targeted on TI platform. Read more...
Codec development and Framework Abstract: HSC has a vast experience in Multimedia codec development and optimization on various processors. We developed the multimedia framework where we have integrated the developed and optimized codecs in the framework. The codecs were optimized to meet the MCPS and Memory requirement. Read more...
3G baseband development Abstract: This project was to develop the baseband receiver using TI C64X DSP and Xilinx FGPGA. We developed the front end receiver algorithms including rake receiver. We also developed the state machine and scheduler for Baseband processing which was placed in ARM 9. Read more...
RTL implementation of L1 datapath as per 3GPP LTE Rel 8 specifications Abstract: HSC developed a Layer 1 processing solution targeted on FPGA. The RTL code was developed to meet the throughput and latency requirements of 3GPP LTE. The RTL blocks for layer 1 processing were developed to be used as a coprocessor which can be easily integrated with a processor to schedule layer 1 processing. Read more...
DVB-s2 satellite modem Abstract: The architecture below comprises of a Broadband VSAT system consisting of FPGAs having interface with DSP & custom SoC. The Adaptive coding and modulation (ACM) feature means that the coding (FEC rate) and modulation DVB-S2 outbound carrier can be dynamically modified to optimize the performance per terminal. Read more...
RTL verification of OBSAI RP3 Interface Abstract: Open Base Station Architecture Initiative (OBSAI) is an industry standard baseband and RF unit interface. HSC developed a top level verification plan and identified test cases to verify the interface and functionality of OBSAI RP-3 core targeted on the Xilinx Virtex 5 device. Customer Benefits: Experience in developing automated verification environment Identified possible test cases based on system requirement definition Worked in offshore model Read more...
3G Layer 1 development Abstract: This project was to develop a baseband receiver using TI C64X DSP and Xilinx FPGA. HSC developed the front end receiver algorithms including rake receiver. To test this HSC developed the UT simulator apart from test vectors generated through MATLAB. Finally to meet the requirement of number of users and throughput HSC also incorporated optimizations in FPGA and DSP. Customer Benefits: Provided reusable components for FPGA. System engineers helped with smooth integration HSC provided DSP, FPGA, System, Algorithms so that the customer could treat HSC as a one stop shop and not have to mediate between multiple customers. Read more...